30 Nisan 2013 Salı günü, saat 14.00'da FBE F-17 salonunda Dr. Hakan Doğan'ın konuşması gerçekleşecektir. Etkinliğe bölümümüz öğretim elemanları ve sadece 4. sınıf lisans öğrencileri davetlidir.
Konuşmacının kısa geçmişi ve konuşmanın özeti aşağıda İngilizce olarak verilmiştir.
Short Biography:
Hakan Dogan was born in Malatya, Turkey on June 6, 1976. He received the B.S. degree in electrical engineering from University of Southern California (USC), Los Angeles, in 1999, and the M.S. and Ph.D. degrees in electrical engineering from the University of California at Berkeley in 2001 and 2005, respectively. During his PhD, he worked with Prof. Robert G. Meyer where he analyzed and designed CMOS Attenuators for radio frequency applications.
He has been with Qualcomm-Atheros, San Jose, CA for the last two years, where he is involved with dual-band wireless-LAN transceiver, Bluetooth transceiver, PLC transceiver and GPS receiver chipset designs. Before its acquisition by Qualcomm Inc., he was with Atheros Communications from 2005 to 2011 working on similar products. In the summer of 2000, he worked in HP Labs, where he was involved with the design of clock and data recovery circuits for high-speed serial data links. During the two consecutive summers, in 2001 and 2002, he was with Maxim Integrated Circuits, where he was involved with the design of cable modem tuners and satellite receivers.
Dr. Dogan is a member of various honor societies and recipient of various awards.
Abstract:
In this talk, recent work by the speaker which gives details about a 3x3 MIMO WLAN SoC wll be presented.
The rapid commercialization of the IEEE 802.11n WLAN standard has increased the demand for higher data-rate and longer-range fully integrated MIMO SoCs that are backward-compatible with legacy IEEE 802.11a/b/g networks. This paper introduces a 3-stream, 3x3 MIMO WLAN SoC that utilizes three antennas to improve throughput, range, and link robustness. This chip integrates three dual-band transceivers, digital physical layer, media access controller, and a PCI express interface in a 65nm CMOS process. Improved EVM is achieved by reducing transmit and receive l/Q mismatch with calibration, and reducing the integrated phase noise with a reference clock doubler.
The speaker will also go over his PhD work on RF CMOS attenuators briefly and will present the highlights.